Drive circuit for digit lines



Dec. 8, 1970 o. ESPINAL 3,546,487

DRIVE CIRCUIT FOR DIGIT LINES Filed April 15, 1966 2 SheetsSheet 2 I N VE N TOR. fiAN/EL ESP/MIL United States Patent r 3,546,487 DRIVE CIRCUIT FOR DIGIT LINES Daniel Espinal, Franklin, Mass., assignor to RCA Corporation, a corporation of Delaware Filed Apr. 15,1966, Ser. No. 542,801 Int. Cl. Gllc 5/02, 7/00; H03k 1/00 US. Cl. 307-270 1 Claim ABSTRACT OF THE DISCLOSURE This invention relates to pulse circuits, and particularly to circuits for driving a current pulse of standardized amplitude through a line including inductance. While not limited thereto, the invention is particularly useful for driving a current pulse through a digit or inhibit line of a memory including an array of magnetic memory elements such as magnetic cores.

A magnetic memory customarily consists of an array of magnetic memory elements linked by selection lines (word lines or X-Y lines) and linked by information-inserting lines (digit lines or inhibit lines). A separate sense line may also be included, or the digit lines may be used also for sense signals. When information is written into the memory, the digit or inhibit lines are driven or not driven, in accordance with the information digits to be stored, by respective transistor digit drivers. It is desirable that each digit driver supply a current pulse through its respective digit line which has a steep leading edge and which has a standardized maximum amplitude. The steep leading edge of the digit driver output pulse is customarily provided by employing a relatively high bias potential source to overcome the inductive effect of the magnetic elements linked by the digit line. The standardized maximum amplitude of the digit driver output pulse is obtained by employing a relatively large resistor in series with the digit line.

It is a general object of this invention to provide an improved digit driver having improved efiiciency and greatly reduced power dissipation.

According to an example of the invention, a digit driver includes a first potential source connected through a first transistor current switch to one end of the memory digit line to be driven. A second relatively low potential source is connected through a unidirectional conduction device or rectifier to the same one end of the digit line. The other end of the digit line is connected through a second transistor current switch to a return path of the potential sources. The first transistor is initially rendered conductive to charge the digit line to the potential of the first potential source. The second transistor is rendered conductive before the first transistor is turned off. During the time that both transistors are conductive, a steeply-rising current is made to flow through the digit line. After the first transistor is turned off and during the time that the second transistor remains on, a continuing standardized current flows from the second potential source, through the unidirectional current device, through the digit line and through the second transistor.

In the drawing:

FIG. 1 is a circuit diagram of a prior art digit driver;

3,546,487 Patented Dec. 8, 1970 FIG. 2 is a circuit diagram of a digit driver constructed according to the teachings of this invention;

FIG. 3 is a block diagram of a system for generating two-timeoverlapping pulses for application to the two transistor switches in the digit driver of FIG. 2;

FIG. 4 is a chart of voltage and current relationships which will be referred to in describing the operation of the digit driver of FIG. 2; and

FIG. 5 is a circuit diagram like FIG. 2 but showing exemplary current switches in greater detail.

Referring now in greater detail to the drawing, FIG. 1 shows a prior art digit driver for one digit line D in a magnetic memory array of magnetic cores M. The magnetic cores linked by the digit line D present an inductance L which must be overcome in initiating a current through the digit line. The prior art digit driver includes a potential source terminal +V' connected through the digit line D, through a resistor R, and through the current-path electrodes of a transistor switch Q to a return path of the potential source. The transistor Q is normally non-conductive, and is rendered fully conductive by a pulse C connected to the control electrode '10 of the transistor Q.

The prior art circuit of FIG. 1 requires a high potential +V source, having a value typically of 55 volts, in order to overcome the effect of inductance L and provide a steeply-rising current pulse through the digit line D. The prior art circuit also requires a resistor R, having a value typically of ohms, for the purpose of limiting the amplitude of the current pulse flowing through the digit line D after a steeply-rising buildup of current has been established in the digit line D. The continuing current flowing through the resistor R results in the dissipation of power in the resistor in the form of heat. The amount of power dissipated in the resistor R is about four times as great as the power usefully dissipated in accomplishing the switching of magnetic cores M linked by the digit line D.

It is also known in the prior art to use a digit driver constructed to continuously supply a value of current which is normally steered into a dissipating current sink, and which is steered when needed through a digit line of a memory. Such a known current-steering arrangement is wasteful of current in that only a small proportion of the continuously generated current is usefully applied to the memory. The wasted current is expensive to generate, and its dissipation results in the generation of undesired heat which must be removed.

FIG. 2 shows a digit driver circuit according to the invention. A V terminal of a first potential source is connected through the current-path electrodes of a first transistor current switch Q to one end of the digit line D. The transistor Q is normally nonconducting and is rendered fully conductive by the application to its control electrode 11 of a positive pulse C A V terminal of a second potential source is connected through a unidirectional current device or rectifier CR to the same end of the digit line D The first source terminal V may have a potential of ;+l2 volts and the second potential terminal V may have a potential of +6 volts.

The other, lower end of the digit line D, is connected through the current-path electrodes of a second transistor current switch Q, to a return path of the potential sources having terminals V and V The transistor Q is normall; nonconducting and is rendered fully conducting by the application to its control electrode 12 of a positive pulse FIG. 3 shows an exemplary arrangement for providing two time-overlapping pulses to respective transistors Q and Q in FIG. 2. The arrangement of FIG. 3 includes an input terminal 13 connected to three series-connected delay means D D and D A first flip-flop FF has a set input coupled to the input terminal 13, and has a reset input coupled to the output of delay means D A second flip-flop FF has a set input connected to the output of delay means D and has a reset input coupled to the output of delay means D The 1 output of flip-flop FF provides an output for connection to terminal 11 in FIG. 2, and the 1 output of flip-flop FF provides an output for connection to terminal 12 in FIG. 2.

FIG. 4a is a chart showing the voltage pulse C applied to the control electrode 11 of transistor Q FIG. 4b is a chart showing a time-overlapping voltage pulse C applied to the control electrode 12 of transistor Q FIG. 4c is a chart showing the resulting current I which flows through the digit line D in FIG. 2.

In operation, the system of FIG. 3 responds at time t to the leading edge of an input pulse 14 applied to input terminal 13 to set the flip-flop FF At a later time t determined by the delay device D the flip-flop FF is set.

At a still later time t determined by the delay device D the flip-flop FF is reset to terminate its output pulse C Finally at a time t determined by the delay device D the fiip-flop FF is reset to terminate its output pulse C As shown in FIGS. 4a and 4b, the pulses C and C overlap in time, and pulse C continues for a period following termination of pulse C The operation of the digit driver circuit of FIG. 2 will now be described. The leading edge of the pulse C applied to the control terminal 11 of transistor Q causes the transistor to be rendered fully conductive. This connects the potential of source V to one end of the digit line D Since the transistor Q is still nonconducting, current cannot flow through the digit line D but a charging current can and does flow into the digit line D to raise its potential to the potential of source V While transistor Q is turned on, at time 1 transistor Q is also turned on by pulse C applied to its control terminal 12. Current then starts flowing through the digit line D in a rapidly increasing manner determined by the value of the inductance L presented by the magnetic cores linked with digit line D The inductance L may typically have a value of micro-henries. The increasing current is given by the formula:

where R; is the resistance in the series path from terminal V to ground. The value of resistance R is relatively low and is determined primarily by the resistance of the digit line D The resistance of digit line D may be accurately controlled by employing Nichrome wire trimmed to a length provided a desired standardized value of resistance.

Since the resistance R of digit line D is small compared with the resistance R in the prior art circuit of FIG. 1, the current in digit line D in FIG. 2 builds up rapidly and if continued would asymptotically approach an undesirably-large current value equal to V /R Advantage it taken of the steeply-rising current, and then, when a desired current amplitude is reached at time t the transistor Q is turned off by the trailing edge of the pulse C applied to its control terminal. The desired value of current then continues to flow through the digit line D from the second potential source V The shutting off of the transistor Q removes the back bias from the rectifier CR so that it becomes conductive in passing current from terminal V through the digit line D and through the second transistor Q to ground. The lower voltage of the source V is sufircient to maintain a continuing current flow through the digit line D because the inductance L does not affect or resist a constant or unchanging current flow. The relatively low voltage of the second potential source V combined with the absence of appreciable resistance in circuit with the digit line D results in the maintenance of the desired current without an undesired dissipation of energy in a resistor such as the resistor R in the prior art circuit of FIG. 1.

The described standardized value of current continues to flow from the time t to the time t at the trailing edge of the pulse C applied to transistor Q The current flow through the digit line D is thus a current pulse as represented in FIG. 40.

FIG. 5 is a digit driver circuit in which the current switches Q and Q of FIG. 2 are shown in greater detail. The upper current switch in FIG. 5 is a conventional current switch including transistors Q and Q which respond to an input pulse at terminal 11. The lower current switch is a conventional switch including transistors Q and Q which respond to an input signal at terminal 12.

The digit driver circuits of FIGS. 2 and 5 involve a power dissipation which is from seventy to ninety percent less than the power dissipation in a prior art circuit according to FIG. 1. About forty percent of the total power dissipation in a magnetic memory is due to power dissipation in the digit driver circuits. Therefore, the reduced power dissipation afforded by digit drivers according to the invention permit a very significant reduction in the overall power dissipation of a complete memory system.

What is claimed is:

1. A driver for a digit or inhibit line of a magnetic memory, comprising a first potential source and a first transistor switch having a control electrode and having current-path electrodes coupling said first potential source to one end of said line,

a second lower potential source, and a unidirectional current device coupling the second potential source to said one end of said line,

a second transistor switch having a control electrode and having current-path electrodes coupling the other end of said line through a return path to said potential sources,

means to apply a first pulse to the control electrode of said first switch to connect said first potentialsource to said line to cause an initial charging of the line to the potential of the first potential source, and

means to apply a second pulse to the control electrode of said second switch, said second pulse starting at a time intermediate the beginning and end of the first pulse and ending at a time following the end of the first pulse, to cause an initial current flow through the line from the first potential source, and then to cause a continuing current flow in the same direction through the line from the second potential source.

References Cited UNITED STATES PATENTS JAMES W. MOFFITT, Primary Examiner U.S. Cl. X.R. 

